Overview
We have had a fantastic opportunity come available for a Senior Hardware Verification Engineer F/H in France.
Role
ROLE:
Senior Hardware Verification Engineer (H/F)
Location
LOCATION:
Sophia Antipolis, France
Duration
DURATION:
Permanent
Salary
SALARY:
Negotiable
Overview
This is an exciting opportunity to join an innovative, fast-paced environment working on cutting-edge hardware IP development.
As a Senior Hardware Verification Engineer, you will contribute to the design quality and robustness of complex and highly configurable IPs.
You will work alongside experienced design and architecture teams, driving the verification process end-to-end.
Responsibilities
- Define, document, develop, and execute RTL verification tests and coverage for highly parameterized IPs using Python and C++.
- Ensure compatibility across industry-standard RTL simulators (e.g.,
Cadence, Synopsys).
- Maintain and enhance the verification workflow, improve metrics, and increase test automation.
- Develop and implement verification components such as Bus Functional Models (BFMs) and monitors.
- Collaborate closely with cross-functional teams to identify and resolve design and verification issues.
Qualifications
- Minimum of 4 years of professional experience in hardware verification.
- Proficient in RTL design and verification languages:
VHDL, Verilog, SystemVerilog, SystemC, Python, and C++.
- Experience with UVM methodology, VIPs, testbenches, and EDA tools.
- Familiarity with formal proof verification techniques is a plus.
- Proficiency in shell scripting and working within Linux environments.
- Good understanding of interconnect technologies and hardware communication protocols (AMBA, OCP, etc.).
- Excellent written and verbal communication skills in both French and English.
- Independent, quality-driven, and highly collaborative team player.
Education
Education requirements:
Master’s degree or PhD in Engineering, Computer Science, or a related technical field.
If interested, please get in touch.
