Exciting opportunity for a SeniorVerificationEngineer in Sophia Antipolis, France to lead UVM verification of cutting:
edge SoC and FPGA IPs with a top semiconductor company.
Job Title:
SeniorVerificationEngineer
Location:
Sophia Antipolis, France
Contract Type:
Permanent
Company Overview:
Join a leading semiconductor company at the heart of the French Riviera, driving innovation in hardware design and verification.
Be part of a dynamic R and D team working on cutting:
edge SoC and FPGA projects that shape the next generation of chips.
Role Overview:
We are looking for a SeniorVerificationEngineer to take ownership of UVM:
based verification flows, lead the verification of complex hardware IPs, and collaborate closely with design, architecture, and software teams on high:
profile projects.
Key Responsibilities:
:
Lead and execute RTL and UVM verification flows for complex hardware IPs.
:
Work closely with design, architecture, and software teams to ensure robust verification coverage.
:
Develop and maintain testbenches, verification plans, and coverage models.
:
Implement and maintain verification automation scripts.
:
Participate in design reviews, provide feedback, and drive verification best practices.
Requirements:
:
Strong RTL and UVM verification experience.
:
Proficiency in Verilog, SystemVerilog, and VHDL.
:
Experience with simulation tools such as Questa, VCS, or Xcelium.
:
Familiarity with SoC IPs such as Ethernet, USB, DDR.
:
Scripting skills in Python and TCL; experience with Unix/Linux environments.
:
Proficiency with Git and collaborative workflows.
:
Fluent English; French is a plus.
:
Master's degree or equivalent in Electrical or Computer Engineering.
Why This Role is Exciting:
:
Opportunity to work in the French Riviera tech hub.
:
Contribute to innovative SoC and FPGA projects with real:
world impact.
:
Join a collaborative team driving hardware innovation.
If this opportunity sounds interesting, please get in touch and share your CV with me at microTECHGlobal Ltd Engineering CDI market rate
