offre-emploi


Senior physical design engineer (W/M) > Joboolo FR :


Société : RHESO.TECH
Lieu : Paris

Senior Physical Design Engineer (W/M) Contract Type:

Full-time (CDI) Location:

Paris Ref:

1283 Contact:

Recruiting Company:

French fabless semiconductor manufacturer specialized in the design and marketing of highly integrated, mixed-signal semiconductor products for markets demanding wideband and low power analog-to-digital, digital-to-analog conversion.

Role:

The Design Team is looking for a dynamic and highly motivated Physical design engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.

The candidate will execute the backend process through the entire RTL-to-GDSII flow.

Responsibilities:

Lead the physical implementation from RTL to GDSII of a complex ASIC in advanced CMOS process (max 22nm).

Collaborate closely with the RTL design team to comprehend digital architecture and execute physical design.

Contribute to defining and refining the physical implementation flow.

Manage floorplan, pin placement, power planning, and block/top-level assembly.

Contribute to defining the supply strategy and selecting standard cells.

Develop timing budgets and draft power intent (SDC) based on design information and specifications.

Ensure timing and physical closure, incorporating lithography optimizations.

Conduct Quality Assurance checks (DRC, LVS, equivalence, power intent checking).

Perform Quality of Result checks, including signoff timing and power analyses.

Integrate DFT scan functionality and contribute to evaluating the fabricated ASIC in the measurement lab.

Collaborate within a team for the successful design of a state-of-the art ASIC.

Participate in design reviews and document processes in accordance with company QA policy.

Requirements:

You hold an MSc or PhD in Electrical Engineering or equivalent, with over 10 years of hands-on experience in physical design of digital IC from RTL to GDSII, and knowledge of scripting languages (TCL/Python/Bash/Make).

Must have physical design flow experience:

Cadence, full RTL to GDS2 execution with 22 nm and below.

Could haves:

large designs, advanced CMOS technologies and high clock speed, physical implementation of digital processing functions for Mixed-Signal ICs such as A/D Converters, D/A Converters, and/or RF transceivers.

You demonstrate analytical and problem-solving skills, are a team player with a critical attitude and sense of initiative, communicate fluently in oral and written English.

Education:

BAC5, Master's Degree, Engineering School RHESO.TECH, a specialized recruitment agency https:

//www.rheso.tech/ Key words:

Design, CMOS, ASIC, RTL, DGSII, Cadence, Converter, Transceiver, DFT
RHESO.TECH
Paris
permanent
Expérience souhaitée




Nouvelle recherche d'emploi Senior physical design engineer (W/M)

Plus d'offres RHESO.TECH

Senior physical design engineer (W/M) - Lieu : Caen - Société : RHESO.TECH

Senior physical design engineer (W/M) - Lieu : Paris - Société : RHESO.TECH

Senior physical design engineer (W/M) - Lieu : Grenoble - Société : RHESO.TECH







Offres d'emploi fournis par offre-emploi ==> France