Our client are an international semiconductor company who specialise in Network:
on:
Chip (NoC)
Brief:
As a Performance Modeling Engineer, you will work with an expert team to design and deliver interconnect and memory hierarchy solutions for some of the worlds most sophisticated mobile, telecom, automotive, and consumer SoC products.
You will model complex configurable designs and produce performance analyses that drive architectural decisions.
Responsibilities:
Track state:
of:
the:
art developments in novel storage technologies;
Be collaborative in developing and prototyping end:
to:
end solutions with researchers within the group, researchers and engineers elsewhere in the company, as well as with external researchers in the open source community, universities, and other labs;
Contribute to the state:
of:
the:
art developments in novel storage system research, preferably by contributing to the corresponding open software frameworks and by publishing high quality material in renowned academic conferences and journals.
Experience Required:
Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
7+ years of experience in developing software performance models in one or more of the following:
CPUs, GPUs, networking on chip, or equivalent.
7+ experience in driving architecture and microarchitecture improvements using performance model analyses.
7+ years' experience in SystemC, C++, and/or TLM2.0.
Strong problem solving, debugging, and brainstorming skills.
Fluent in English and French
Desirables:
Familiarity with ARM processors and on:
chip interfaces such as OCP and AXI.
Strong knowledge of cache coherency protocols.
Experience with code generators to create configurable hardware descriptions.
Experience with scripting languages such as TCL/Perl/Python etc.
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