We are looking for an experienced and highly motivated engineer to join one of the hardworking and high performing teams within Systems Engineering! In this role you will work closely with IP and systems teams across Arm to benchmark performance results and analysis to assist in ultimately helping to build high-performance System IPs and Interconnects! This role is for the Interconnect product team.
If the following job requirements and experience match your skills, please ensure you apply promptly.
The Interconnect team develops the Arm Core link Interconnect IP family.
Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including mobile, IoT, networking infrastructure, automotive etc.
The highly scalable IP is optimized for AMBA-compliant SoC connectivity and can be customised for multiple performance points.
Responsibilities:
Engage with architects and design teams to build end to end test cases in C++/Python/System Verilog targeting performance bottle necks in products such as System MMU and Network-On-Chip Interconnect Analyze design and identifying performance issues and improving the correlation of models against RTL To provide methodical benchmark result synthesis, analysis and presentation to wider team.
Close collaboration with other Arm engineering teams leading to highly performance efficient IP that works well in a complete system.
Support and collaborate with other teams building system level simulations using a range of models Building infrastructure for use in performance analysis to enable better inspection and visibility of performance in Systems IP Helping to define strategic direction of system performancemodelling across Arm Essential skills and experience:
Strong at C++ programming for large-scale software development and experience with RTL/emulation performance analysis and correlation.
Experience in performance verification or modelling.
Strong computer architecture knowledge Perl or Python scripting language skills 'Nice to Have' Skills and Experience:
CPU or compute subsystem memory micro-architecture Working knowledge of common on-chip bus protocols such as AMBA Knowledge of System C Transaction Level Modelling would be a plus.
